Software Defined Radio (SDR) is defined as "Radio in which some or all of the physical layer functions are software defined". SDR defines a collection of hardware and software technologies where some or all of the radios operating functions (also referred to as physical layer processing) are implemented through modifiable software or firmware operating on programmable processing technologies. It is a radio that has the ability to be transformed through the use of software or re-definable logic. They have the ability to go beyond simple single channel, single mode transceiver technology with the ability to change modes arbitrarily because the channel bandwidth, rate, and modulation are all flexibly determined through software. It takes an AM/FM modulated signal from a common RF front end, down convert to baseband frequency and then demodulates it.
Recent advancement in semiconductor technology has allowed traditional analog radio systems to be realized with today's digital circuit technology. Software Defined Radio (SDR) is a new digital technology wherein radio functions are implemented by signal- processing software running on generic hardware platforms. This makes the system very flexible and adaptive, and thus promises to solve the many problems faced by traditional hardware based radio systems.
Field Programmable Gate Arrays (FPGA) are increasingly being employed as the hardware platform for building real time signal processing systems due to its performance, power consumption and configurability. The purpose of this project is to investigate Software Defined Radio technology by implementing a digital radio receiver in software running on a FPGA platform. RF modulated signals are digitally sampled and demodulated in real time using digital circuits of the FPGA, which is programmable by the software.
Hardware Block Diagram
The system overview of the digital receiver explaining how SDR technology can be used to implement radio functions in software is given in this section. The various functional blocks in a generic digital radio receiver system is depicted in figure. Radio signals received by an antenna first go through an Anti-Aliasing Filter to remove all signals out of AM/FM bands. This analog filter is necessary in order to avoid aliasing problems in digital implementation. The analog input is then digitized into digital samples by an A/D (analog-to-digital) converter.
From this point, all subsequent operations including mixing, filtering and demodulation is done using digital signal processing techniques to extract radio channels of interest. These operations are supported by key components of the digital receiver including Digital Mixer, Digital Local Oscillator, Digital Low Pass Filter and Digital Demodulation. After demodulation, digital samples of radio channels of interest are converted back to analog format using a D/A (digital-to-analog) converter. The radio signal is amplified and played by a loud speak. The digital radio system consists of three main functional blocks.
RF section, IF section and base band section. The RF section consists of essentially analog hardware modules while IF and base band sections contain digital hardware modules. The digital radio system consists of three main functional blocks: RF section, IF section and base band section. The RF section consists of essentially analog hardware modules while IF and base band sections contain digital hardware modules.
RF Front End
The first stage, called RF Front End can range from an antenna with a wideband low pass filter, up to a complete multi stage receiver where the output is an IF or signal in base band with a specific bandwidth according to the demodulation requirements. Radio signals received by an antenna first go through an Anti-Aliasing Filter to remove all signals out of bands. This analog filter is necessary in order to avoid aliasing problems in digital implementation. Since the RF front-end receives high frequencies used in frequency ranges, RF front-end can not be digital. In this case, of higher frequencies, an analog down-converter is required to translate frequencies (hundreds of MHz to some GHz) to an intermediate frequency (IF) or base band (BB). Thus, RF section is responsible for receiving the radio frequency (RF) signal from the antenna and converting the RF signal to an intermediate frequency (IF) signal.
Analog to Digital Converter
Now the band is down-converted to lower frequency, at this lower frequencies the used bandwidth of channel can be processed in a standard ADC,digitizing it. After the signal is digitized, software can control the channel frequency, bandwidth and modulation format. Placing the ADC as close to the antenna as possible provides the most exibility but must be traded off against performance limitations. An ADC converts an infinite range of analog values to a limited number of digitized values. The performance of sampling process is specified by its impact on noise (SNR) and distortion. Unless a signal is in dc or Fs/2, we cannot know the original input at the ADC output. This was described by Nyquist when he said analog signals must be sampled at more than twice their highest frequency to completely recover the sampled information. Most sampling discussions center on the signals from DC to Fs/2, also known as the first Nyquist zone, because every input to the ADC will appear in the
first Nyquist zone at the ADC output.
All signals sampled by the ADC will be output in the first Nyquist zone (DC to Fs/2) therefore, If there are any unwanted signals (including noise) above Fs/2 they must be filtered prior to sampling. Unwanted signals above Fs/2 can interfere. Once sampled, the unwanted signals cannot be removed Subsampling takes advantage of aliasing to sample narrow-band signals beyond the first Nyquist zone. All the images will appear in the first Nyquist zone at the ADC output. Filtering must be used to select the desired image. It is commonly used for Intermediate Frequency (IF) sampling receivers. The concept of the DDC is to sample the whole input signal and to use digital techniques to reduce the data. However, that may require an unrealistically fast ADC.
For example, Nyquists theory states that we should sample at a rate at least double the bandwidth of interest. If we do this on a 1GHz carrier, we would need an ADC sampling at well over 2GHz; that ADC would be protected by anti-aliasing filters, removing any signal above 1GHz. However, this is beyond what can be achieved with todays technology. The ADC chosen according to our system requirements is AD9245.The AD9245 is a monolithic, single 3 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC) featuring a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate.
The digital down converter section of SDR is configured in the FPGA. The features such as reconfigurability, high parallel processing, special hardware's for some DSP operations, re-programmability, power efficiency makes FPGA based SDRs an excellent platform for creating radios.FPGAs allow their users to define what the system is capabe of and provide resources for massive parallelization. A Field programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the user after manufacturing hence named field programmable. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. Please go through the attached report for detailed implementation.